Serial connection external interface riser cards avoidance of abutment of parallel connection external interface memory modules

ABSTRACT

A first riser card of an apparatus in an example substantially axially connects with a first serial connection external interface of a printed circuit board (PCB) and at least in part laterally connects with a parallel connection external interface of a first memory module. The first riser card supports the first memory module with avoidance of abutment of the first memory module with a second memory module supported by a second riser card that is adjacent to the first riser card.

RELATED APPLICATIONS

This application is a divisional of and claims priority to U.S. patentapplication Ser. No. 13/331,940 filed on Dec. 20, 2011, which is adivisional of U.S. patent application Ser. No. 11/789,632 filed on Apr.25, 2007, all of which are herein incorporated by reference in theirentirety.

BACKGROUND

DIMM (dual in-line memory module) technology has random access memory(RAM) integrated circuits (ICs) mounted on a printed circuit board(PCB). Various types of DIMMs exist. DDR SDRAM (Double Data RateSynchronous Dynamic Random Access Memory) DIMM technology has a parallelexternal interface. Fully buffered DIMM or FB-DIMM technology has aserial external interface.

FB-DIMM technology employs an Advanced Memory Buffer (AMB) having aserial connection to a memory controller, and a parallel connection todynamic random access memory (DRAM). The AMB on each FB-DIMM translatesthe communication in serial point-to-point link protocol received fromthe memory host controller to DDR3 SDRAM parallel protocol transmittedto the DRAMs as read, write, refresh, etc. operations within the DIMM.

The PCB and FB-DIMM are coupled by connectors. The connectors are serialconnection external interfaces. The standard pitch and/orcenter-to-center spacing of the connectors is approximately 0.5 in (12.7mm) or more.

DESCRIPTION OF THE DRAWINGS

Features of exemplary implementations of the invention will becomeapparent from the description, the claims, and the accompanying drawingsin which:

FIG. 1 is a representation of an implementation of an apparatus thatcomprises one or more riser boards and/or cards, a system board and/orprinted circuit board (PCB), one or more serial protocol busses, one ormore parallel protocol memory modules, and one or more parallel protocolbusses.

FIG. 2 is an enlarged, side representation of a riser card of animplementation of the apparatus of FIG. 1.

FIG. 3 is similar to FIG. 2 and represents an exemplary set and/or pairof riser cards of an implementation of the apparatus of FIG. 1.

FIG. 4 is a perspective, cutaway, partial, exploded representation of aplurality of riser cards, a plurality of parallel protocol memorymodules, and the PCB of an implementation of the apparatus of FIG. 1,and illustrates a first exemplary arrangement of the riser cards andparallel protocol memory modules.

FIG. 5 is a top, partial, perspective representation of two riser cardsand two parallel protocol memory modules of the implementation of theapparatus of FIG. 4.

FIG. 6 is similar to FIG. 4 and illustrates a second exemplaryarrangement of the riser cards and parallel protocol memory modules.

FIG. 7 is a top, partial, perspective representation of two riser cardsand two parallel protocol memory modules of the implementation of theapparatus of FIG. 6.

FIG. 8 is similar to FIGS. 4 and 6 and illustrates a third exemplaryarrangement of the riser cards and parallel protocol memory modules.

FIG. 9 is a side, partial representation of two riser cards and fourparallel protocol memory modules of the implementation of the apparatusof FIG. 8, and illustrates an exemplary translator of the riser cards.

FIG. 10 is similar to FIGS. 4, 6, and 8 and illustrates a fourthexemplary arrangement of the riser cards and parallel protocol memorymodules.

FIG. 11 is a side, partial representation of four riser cards and eightparallel protocol memory modules of the implementation of the apparatusof FIG. 10, and illustrates an exemplary translator of the riser cards.

FIG. 12 is a representation of an exemplary logic flow for upgrade of aserial protocol memory implementation to a parallel protocol memoryimplementation of the apparatus of FIG. 1.

DETAILED DESCRIPTION

Referring to the BACKGROUND section above, while the FB-DIMM hasinternal memory with parallel connections, the external interface is aserial connection. With DDR3 SDRAM being a successor to DDR2 SDRAM inDDR memory standards, computer system boards with FB-DIMM connectorsembedded will not be able to support DDR3 SDRAM DIMMs. The serial memoryconnections of FB-DIMM connectors are fundamentally different from theparallel memory connections of DDR3 DRAM DIMM connectors.

FB-DIMMs are based on serial data transfer technology while DDR3 SDRAMDIMMs are based on parallel data transfer technology. An exemplaryimplementation allows both different memory technologies to be used in asame package with no additional cost added to the design of a computersystem board with existing FB-DIMM connectors. The cost of supportingboth memory technologies on a single platform in an example is moved toa translator riser board and/or card. An exemplary translator riser cardcomprises an FB-DIMM-to-DDR3 SDRAM translator IC and DDR3 SDRAM DIMMconnectors. Full memory speed for both FB-DIMMs and DDR3 SDRAM DIMMs inan example is achievable.

An exemplary implementation supports DDR3 SDRAM DIMMs on systems withembedded FB-DIMM connectors without need for additional hardware to bedesigned into the system board. An exemplary approach reducesmodification time, labor, and/or materials through employment of asingle memory technology such as FB-DIMM on the computer system boardwhile at the same time increasing memory capacity of both FB-DIMM andDDR3 SDRAM. A translator in an example serves to communicativelyinterconnect FB-DIMM and DDR3 SDRAM. An exemplary translator comprises atranslator riser board and/or card. The riser card in an examplecomprises a circuit card or board that connects directly to the PCB andallows addition of cards to the PCB by connection through the risercard.

An exemplary implementation provides low cost for DDR3 SDRAM support onFB-DIMM connectors through employment of a translator riser card. Anexemplary approach provides low cost employment of two different typesof memory technology, for example, DDR3 SDRAM DIMMs and FB-DIMMs on asingle platform with existing FB-DIMM connector, for example, throughemployment of a translator riser card. An exemplary translator risercard comprises an FB-DIMM-to-DDR3 SDRAM translator and DDR3 DIMMconnectors. For example, the translator comprises an IC and/or chip. Thetranslator riser card in an example plugs in vertically and/ororthogonally to FB-DIMM connectors and allows DDR3 DIMMs to run directlyfrom the FB-DIMM connectors. An exemplary implementation reducesmodification cost by allowing a single memory technology, for example,FB-DIMM, on the computer system board and/or PCB and contemporaneouslypromoting memory capacity of DDR3 SDRAM FB-DIMM, for example, throughemployment of the translator riser card.

An exemplary riser card plugs directly into a system board with anFB-DIMM connector and allows DDR3 DIMMs on computer systems designed forFB-DIMM memory technology. With a translator riser card in an example noadditional investment is required to allow DDR3 memory technology onsystem boards designed for FB-DIMM memory technology.

An exemplary implementation provides low cost for delivery of DDR3 SDRAMand FB-DIMM memory architecture on a computer system with standardFB-DIMM socket pitch. The standard pitch and/or center-to-center spacingof FB-DIMM connectors on a PCB is approximately 0.5 in (12.7 mm) ormore. An exemplary employment of pairs, for example, alternating and/orstaggered pairs and/or sets, of translator riser cards allows use ofDDR3 SDRAM DIMMs on PCBs with FB-DIMM connectors with standard connectorpitch.

An exemplary implementation allows DDR3 SDRAM DIMMs to run at full speedand with full available bandwidth on a PCB and/or computer systemdesigned for FB-DIMM memory architecture. This remains true for systemswith standard FB-DIMM connector pitch. An exemplary approach provides auser an option of using either FB-DIMM or DDR3 SDRAM DIMMs on a PCBand/or computer system with FB-DIMM connectors.

An exemplary approach removes from the PCB an otherwise additional costof designing into the PCB memory architectures of both FB-DIMM and DDR3SDRAM DIMM. An exemplary approach simplifies a design of the PCB and/orcomputer system so the designer needs to design for only FB-DIMM memoryarchitecture. An exemplary approach moves the added cost and complexityfor DDR3 SDRAM DIMM memory architecture to pairs and/or sets oftranslator riser cards. The translator riser cards in an example fitinto a PCB embedded with FB-DIMM connectors, for example, designed toJEDEC (JEDEC Solid State Technology Association, previously known as theJoint Electron Device Engineering Council; World Wide Web jedec.org)specification and with standard connector pitch, for example, 0.5 in(12.7 mm) or wider. Another exemplary implementation fits and/or insertsthe pairs and/or sets of translator riser cards into FB-DIMM connectorswhere the pitch is less than 0.5 in (12.7 mm).

An exemplary implementation reduces and/or minimizes space required,used, and/or needed on the PCB to support both FB-DIMM and DDR3 SDRAMDIMM. An exemplary approach reduces cost of the PCB by avoiding need foradditional space on the board to support both FB-DIMM and DDR3 SDRAMDIMM. An example implementation allows shipment of PCBs and/or computersystems embedded with FB-DIMM connectors and yet able to support DDR3SDRAM DIMMs without changing the PCB and/or system board. An exemplaryapproach lowers the cost of the computer system by needing only onememory architecture, for example, FB-DIMM to be designed into the PCB.An exemplary approach reduces the cost by shipping the computer systemwith support for only FB-DIMM, for example, shipping without thetranslator riser card. An exemplary implementation maintains memorybandwidth on both FB-DIMM memory architecture and DDR3 SDRAM DIMM memoryarchitecture such as with two DDR3 SDRAM DIMMs per FB-DIMM bus. Anexemplary implementation employs pairs of translator riser cards inalternating and/or staggered FB-DIMM connectors on a PCB. An exemplaryapproach allows use of DDR3 SDRAM DIMMs on a computer system withstandard FB-DIMM connector pitch on the PCB.

An exemplary translator riser card in a pair of translator riser cardscomprises a translator and/or bridge IC and/or chip such as an FB-DIMMto DDR3 SDRAM bridge and one or more DDR3 busses and DDR3 SDRAM DIMMconnectors. In an exemplary implementation, one edge of each translatorriser card comprises gold fingers that fit into a JEDEC standard twohundred forty (240) positions FB-DIMM connector on the PCB.

In an exemplary implementation, a total number of DDR DIMM connectors onthe riser card outside the PCB can be the same as a total number ofFBDIMM connectors on the PCB. An exemplary approach allows a user tochoose between serial and parallel memory technologies without loss in atotal quantity of DDR DIMM modules and FBDIMM modules allowable in thesystem regardless of the memory technology the user and/or customerchooses to use.

Turning to FIG. 1, an implementation of an apparatus 100 in an examplecomprises one or more riser boards and/or cards 102, 302 (FIG. 3), asystem board and/or printed circuit board (PCB) 104, one or more serialprotocol busses 106, one or more and/or a plurality of parallel protocolmemory modules 112, 114, and one or more parallel protocol busses 116,118. The serial protocol bus 106 in an example comprises a high speedserial bus. Exemplary implementations of the serial protocol bus 106comprise industry standard high speed serial busses such as FBD (fullybuffered DIMM; FB-DIMM).

The riser card 102 in an example comprises a serial protocol interface108, a translator 110, and one or more parallel protocol connectorsand/or interfaces 132, 134 (FIGS. 1 and 5). As discussed herein withreference to FIG. 2, the riser card 102 in an example optionallycomprises a connector 202 and/or one or more voltage regulator modules204. The parallel protocol memory modules 112, 114 in an examplecomprise respective parallel protocol connectors and/or interfaces 136,138 (FIGS. 1 and 5) and a plurality of parallel memory devices 122.Exemplary numbers of instances of the parallel protocol memory modules112, 114 on an exemplary riser card 102 comprise any selected and/ordesirable number, for example, two, four, eight, or sixteen parallelprotocol memory modules 112, 114, 402 (FIG. 4), 404 (FIG. 4). Forexplanatory purposes, FIGS. 1-11 illustrate an exemplary implementationthat comprises two parallel protocol memory modules 112, 114, 402 (FIG.4), 404 (FIG. 4) on each riser card 102. As will be appreciated by thoseskilled in the art, an exemplary riser card 102 comprises more than twoparallel protocol memory modules 112, 114, 402 (FIG. 4), 404 (FIG. 4).Exemplary parallel protocol memory modules 112, 114 comprise registeredand/or unbuffered DIMMs, for example DDR3 DIMMs. An exemplary parallelmemory device 122 comprises a dynamic random access memory (DRAM). Theriser card 102 and the parallel protocol memory modules 112, 114 in anexample serve to take a place of, substitute for, and/or provide anupgrade from a serial protocol memory module 128 that comprisesinterface 130 such as a fully buffered dual in-line memory module(FB-DIMM, FBDIMM, and/or FBD).

The PCB 104 in an example comprises a serial protocol interface 124 anda memory controller and/or host controller 126. The serial protocolinterfaces 108, 124, 130 in an example comprise FB-DIMM memory moduleconnectors (FB-DIMM connectors). An exemplary FB-DIMM memory moduleconnector as the serial protocol interface 108, 130 in an examplecomprises two hundred forty (240) pins and/or fingers that comply withstandards of the JEDEC Solid State Technology Association (previouslyknown as the Joint Electron Device Engineering Council; World Wide Webjedec.org).

The pins of an exemplary interface 108 are vertical and/or orthogonal.The pins of another exemplary interface 108 are angled and/or oblique.The serial protocol interface 108 in an example comprises gold pins thatfit directly into an FB-DIMM memory module connector and/or FB-DIMMconnector as the serial protocol interface 124. An exemplary the FB-DIMMmemory module connector as the serial protocol interface 124 comprisesslots and/or holes that receive, engage, mesh, couple, connect, and/ormate with pins as an exemplary interface 108. The riser card 102 in anexample fits directly into the FB-DIMM connector as the serial protocolinterface 124. An edge of the riser card 102 in an example comprisesgold fingers and/or pins that allow the riser card 102 to plug directlyinto the FB-DIMM memory module connector as the serial protocolinterface 124. As discussed herein with reference to FIG. 2, the risercard 102 in an example comprises notches 206, 208 at both ends to allowthe riser card 102 to be accommodated by end latches 410 (FIG. 4), forexample, of a standard FB-DIMM memory module connector as an exemplaryinterface 124.

The bus 106 as an FB-DIMM bus in an example comprises a northbound (NB)path 140 and a southbound (SB) path 142. An exemplary northbound path140 comprises fourteen (14) bit lanes carrying data from memory such asthe parallel protocol memory module 112, 114 to a processor such as thehost controller 126. An exemplary southbound path 142 comprises ten (10)southbound (SB) bit lanes carrying commands and data from the processorsuch as the host controller 126 to memory such as the parallel protocolmemory module 112, 114. An exemplary parallel protocol bus 116, 118comprises a Double Data Rate (DDR) bus, for example, a DDR3 bus.

To allow employment of one or more DDR3 DIMMs as one or more parallelprotocol memory modules 112, 114 on a computer system and/or PCB 104with an existing FB-DIMM connector as the serial protocol interface 124in an example a user need only plug in riser card 102 into the FB-DIMMconnector as the serial protocol interface 124 and install DDR3 SDRAM(Synchronous Dynamic Random Access Memory) DIMMs as the parallelprotocol memory modules 112, 114 at interface 132, 134 on the riser card102. For example, to allow employment of one or more DDR3 DIMMs as oneor more parallel protocol memory modules 112, 114 in an example a userneed only replace an FB-DIMM as the serial protocol memory module 128with the riser card 102, and have the DDR3 SDRAM DIMMs as the parallelprotocol memory modules 112, 114 coupled with the riser card 102. Toallow employment of an FB-DIMM as the serial protocol memory module 128in an example a user need only replace the riser card 102 with theFB-DIMM as the serial protocol memory module 128.

The FB-DIMM to DDR3 translator IC as the translator 110 in an examplereceives commands and read data from the host controller 126 and sendswrite data back to the host controller 126 using the FB-DIMM protocol asa serial memory protocol. The FB-DIMM to DDR3 translator IC as thetranslator 110 in an example translates the FB-DIMM protocol as theserial memory protocol to DDR protocol as a parallel memory protocol tosend transfer commands and read/write data to the DDR3 DIMMs as theparallel protocol memory modules 112, 114. The translator 110 in anexample drives one or more DDR busses as the busses 116, 118.

Turning to FIG. 2, the riser card 102 in an example comprises notches206, 208 at both ends to allow the riser card 102 to be accommodated byend latches (not shown) of a standard FB-DIMM memory module connector asan exemplary interface 124. The riser card 102 in an example optionallycomprises a connector 202 and/or one or more voltage regulator modules204. The connector 202 in an example receives and/or couples with aflying lead cable (not shown) to deliver additional power to the risercard 102, for example, to the voltage regulator module 204. An exemplaryconnector 202 is locatable at any desirable, selected, and/or convenientplace on the riser card 102. The voltage regulator module 204 in anexample is locatable on the card 102 such as to provide additional,extra, and/or sufficient power to the components onboard and/orconnected with the riser card 102. An exemplary voltage regulator module204 serves to generate component and/or bus voltages.

Turning to FIG. 3, the parallel protocol interfaces 132, 134 of theriser card 102 in an example are located at a different set of heightsthan the parallel protocol interfaces 132, 134 of the riser card 302.Referring to FIGS. 3 and 4, parallel protocol memory modules 112, 114 inan example comprise respective parallel protocol interfaces 136, 138that mate and/or connect with the parallel protocol interfaces 132, 134of the riser card 102 at a first set of heights. The parallel protocolmemory modules 402, 404 in an example comprise respective parallelprotocol interfaces 136, 138 that mate and/or connect with the parallelprotocol interfaces 132, 134 of the riser card 302 at a second set ofheights.

The riser cards 102, 302 in an example comprise a pair and/or set ofriser cards, for example, that point inward and/or toward each otherwith the parallel protocol memory modules 112, 114 and the parallelprotocol memory modules 402, 404 overlapping in a transverse and/orlateral direction relative to the PCB 104 without clashing, colliding,and/or abutting. Overlapping of DDR3 SDRAM DIMMs as a set of theparallel protocol memory modules 112, 114 and a set of the parallelprotocol memory modules 402, 404 in an example serves to increase and/orpromote available space for DIMMs insertion on the PCB 104 and the risercards 102, 302, for example, allowing for standard pitch FB-DIMMconnectors as the serial protocol interfaces 108, 124.

The different heights of the parallel protocol interfaces 132, 134 ofthe riser cards 102, 302 in an example allow employment of standard,reduced, and/or close pitch FB-DIMM connectors as the serial protocolinterfaces 108 of the riser cards 102, 302 and the serial protocolinterfaces 124 of the PCB 104. An exemplary standard pitch FB-DIMMconnectors comprises a pitch of 0.5 in (12.7 mm) or wider. The differentheights of the parallel protocol interfaces 132, 134 of the riser cards102, 302 in an example allow employment of DDR3 SDRAM DIMMs as theparallel protocol memory modules 112, 114, 402, 404 supported on theriser cards 102, 302 and coupled with FB-DIMM connectors as the serialprotocol interfaces 124 of the PCB 104. The different heights of theparallel protocol interfaces 132, 134 of the riser cards 102, 302 in anexample allow the PCB 104 and the riser cards 102, 302 or the serialprotocol memory module 128 as a computer memory subsystem to operate atfull bandwidth and speed on of the DDR3 SDRAM DIMM memory architectureor the FB-DIMM memory architecture.

The serial protocol interfaces 108 of a plurality of riser cards 102,302 in an example are inserted directly into a respective plurality ofFB-DIMM connectors as the serial protocol interfaces 124 on the PCB 104.Referring to FIGS. 1, 4, and 5, DDR3 SDRAM memory as parallel protocolmemory modules 112, 114, 402, 404 in an example have respectiveinterfaces 136, 138 inserted on respective DDR3 DIMM connectors as theparallel protocol interfaces 132, 134 of the riser card 102. The PCB 102in an example is embedded with FB-DIMM memory technology as a serialmemory protocol implementation such as through employment of the hostcontroller 126 and the serial protocol interfaces 124. An exemplaryconnector-to-connector distance 406 between adjacent and/or successiveinterfaces 124 comprises approximately 0.5 in (12.7 mm) or less, forexample, to conform to a standard connector pitch. Another exemplaryconnector-to-connector distance 406 between adjacent and/or successiveinterfaces 124 comprises approximately 0.5 in (12.7 mm) or more. Anexemplary distance 408 between first and fourth, skipping two inbetween, serial protocol interfaces 124 comprises approximately 1.5 in(38.1 mm). Referring to FIG. 5, the distance 408 in an example comprisesan exemplary total depth of a pair of adjacent riser cards 102, 302 withthe parallel protocol memory modules 112, 114, 402, 404 that comprisesapproximately 1.5 in (38.1 mm).

Referring to FIG. 5, an exemplary interface 132 comprises a latch thatpivots into a holding gap as an exemplary interface 136. An exemplarylatch as the interface 132 comprises a standard DIMM connector and/orsocket latch. An exemplary depth 502 of the riser card 102, 302comprises approximately 1.4 in (35.56 mm). An exemplary depth 504 of theparallel protocol memory module 112, 114, 402, 404 comprisesapproximately 1.2 in (30.48 mm). Referring to FIG. 7, an exemplaryspacing, separation, and/or distance 702 between the riser cards 102,302 comprises approximately 0.3 in (7.62 mm). An exemplary total depth704 of a pair of adjacent riser cards 102, 302 with the parallelprotocol memory modules 112, 114, 402, 404 comprises approximately 1.7in (43.18 mm).

Referring to FIGS. 1-7, exemplary interfaces 132, 134, 136, 138 arevertical and/or orthogonal. An exemplary DDR-DIMM interface as theinterface 132, 134, 136, 138 in an example comprises connection of twohundred forty (240) pins and/or fingers that comply with standards ofthe JEDEC Solid State Technology Association (previously known as theJoint Electron Device Engineering Council; World Wide Web jedec.org).Referring to FIGS. 1-3 and 8-11, further exemplary interfaces 132, 134,136, 138 are angled and/or oblique. An exemplary angle 902 comprisesapproximately twenty (20) to thirty (30) degrees, for example,twenty-five (25) degrees, relative to a supporting face of the risercard 102, 302. An exemplary connector-to-connector distance 802 betweenadjacent and/or successive interfaces 124 comprises approximately 0.45in (11.43 mm) or less, for example, to conform to a standard and/orreduced connector pitch. An exemplary distance 804 between first andfourth, skipping two in between, serial protocol interfaces 124comprises approximately 1.35 in (34.29 mm). Referring to FIG. 9, anexemplary total depth 904 of a pair of adjacent riser cards 102, 302with the parallel protocol memory modules 112, 114, 402, 404 comprisesapproximately 0.9 in (22.86 mm). An exemplary depth 906 of the risercard 102, 302 comprises approximately 0.8 in (20.32 mm). Referring toFIG. 10, an exemplary distance 1002 between second and fourth, skippingone in between, serial protocol interfaces 124 comprises approximately 1in (25.4 mm), for example, to conform to a standard connector pitch.Referring to FIG. 11, an exemplary distance 1102 between second andfourth, skipping one in between, serial protocol interfaces 124comprises approximately 0.9 in (22.86 mm).

An illustrative description of an exemplary operation of animplementation of the apparatus 100 is presented, for explanatorypurposes. FIG. 12 is a representation of an exemplary logic flow 1202for upgrade of a serial protocol memory implementation 106, 126 to aparallel protocol memory implementation 110, 116, 118. The logic flow1202 in an example is performed by a user, a consumer, an on-siteservice technician and/or provider, and/or an in-shop service technicianand/or provider. STEP 1204 in an example proceeds to perform an upgradea serial protocol memory implementation 106, 126 within a printedcircuit board (PCB) 104 to a parallel protocol memory implementation110, 116, 118 outside the PCB 104. STEP 1206 employs a first riser card102. STEP 1208 supports a first memory module 112, 114 with the firstriser card 102. The first memory module 112, 114 employs the parallelmemory implementation 110, 116, 118. STEP 1210 plugs the first risercard 102 into a first serial connection external interface 124 of thePCB 104.

An exemplary implementation comprises a first riser card 102 thatsubstantially axially connects with a first serial connection externalinterface 124 of a printed circuit board (PCB) 104 and at least in partlaterally connects with a parallel connection external interface 136,138 of a first memory module 112, 114. The first riser card 102 supportsthe first memory module 112, 114 with avoidance of abutment of the firstmemory module 112, 114 with a second memory module 402, 404 supported bya second riser card 302 that is adjacent to the first riser card 102.

The second riser card 302 substantially axially connects with a secondserial connection external interface 124 of the PCB 104 and electricallyand at least in part laterally connects with a parallel connectionexternal interface 136, 138 of the second memory module 402, 404. Thesecond riser card 302 supports the second memory module 402, 404 withavoidance of abutment of the second memory module 402, 404 with thefirst memory module 112, 114.

The first riser card 102 comprises a first parallel protocol interface132, 134 that connects with the parallel connection external interface136, 138 of the first memory module 112, 114 at a first height relativeto the PCB 104. The second riser card 302 comprises a second parallelprotocol interface 132, 134 that connects with the parallel connectionexternal interface 136, 138 of the second memory module 402, 404 at asecond height relative to the PCB 104. The first and second parallelprotocol interfaces 132, 134 face toward each other and the first andsecond parallel protocol memory modules 112, 114, 402, 404 overlap froma perspective from the PCB 104 without abutment of the first and secondparallel protocol memory modules 112, 114, 402, 404. The first andsecond parallel protocol interfaces 132, 134 face in a substantiallysame direction and the first and second parallel protocol memory modules112, 114, 402, 404 overlap from a perspective from the PCB 104 withoutabutment of the first and second parallel protocol memory modules 112,114, 402, 404.

The first and second parallel protocol memory modules 112, 114, 402, 404are angled between twenty and thirty degrees relative to the respectivefirst and second riser cards 102, 302. The first and second parallelprotocol memory modules 112, 114, 402, 404 overlap from a perspectivefrom the PCB 104 without abutment of the first and second parallelprotocol memory modules 112, 114, 402, 404.

The first and second serial connection external interfaces 124 of thePCB 104 are separated by 0.5 in (12.7 mm) or less. The first and secondserial connection external interfaces 124 of the PCB 104 are separatedby 0.5 in (12.7 mm) or more.

The first riser card 102 communicates between the first serialconnection external interface 124 of the PCB 104 and the parallelconnection external interface 136, 138 of the first memory module 112,114. The first riser card 102 comprises a translator 110 that throughthe serial connection external interface 124 of the PCB 104 and theparallel connection external interface 136, 138 of the first memorymodule 112, 114 communicates between a serial memory protocol within thePCB 104 and a parallel memory protocol within the first memory module112, 114.

The first riser card 102 comprises a translator 110 that through theserial connection external interface 124 of the PCB 104 and the parallelconnection external interface 136, 138 of the first memory module 112,114 communicates between a fully buffered dual in-line memory module(FB-DIMM) protocol within the PCB 104 and a double data rate synchronousdynamic random access memory (DDR SDRAM) protocol within the firstmemory module 112, 114. The DDR SDRAM protocol comprises a DDR3 SDRAMprotocol. The translator 110 through the serial connection externalinterface 124 of the PCB 104 and the parallel connection externalinterface 136, 138 of the first memory module 112, 114 communicatesbetween the FB-DIMM protocol within the PCB 104 and the DDR3 SDRAMprotocol within the first memory module 112, 114.

The first riser card 102 comprises a translator 110 that through theserial connection external interface 124 of the PCB 104 and the parallelconnection external interface 136, 138 of the first memory module 112,114 communicates between an FB DIMM protocol within the PCB 104 and theparallel memory protocol within the first memory module 112, 114. Thefirst riser card 102 comprises a translator 110 that through the serialconnection external interface 124 of the PCB 104 and the parallelconnection external interface 136, 138 of the first memory module 112,114 communicates between the serial memory protocol within the PCB 104and a double data rate (DDR) memory protocol within the first memorymodule 112, 114. The DDR memory protocol comprises a DDR3 SDRAMprotocol. The translator 110 through the serial connection externalinterface 124 of the PCB 104 and the parallel connection externalinterface 136, 138 of the first memory module 112, 114 communicatesbetween the serial memory protocol within the PCB 104 and the DDR3 SDRAMprotocol within the first memory module 112, 114.

An exemplary approach performs an upgrade of a serial memoryimplementation 106, 126 within a printed circuit board (PCB) 104 to aparallel memory implementation 110, 116, 118 outside the PCB 104 throughemployment of a first riser card 102 plugged into a first serialconnection external interface 124 of the PCB 104. The first riser card102 supports a first memory module 112, 114 that employs the parallelmemory implementation 110, 116, 118.

The PCB 104 is provided to a user as a field deployment of the PCB 104with a fixed distance between the first serial connection externalinterface 124 of the PCB 104 and a second serial connection externalinterface 124 of the PCB 104. The first riser card 102 is plugged intothe first serial connection external interface 124 of the PCB 104 afterthe field deployment of the PCB 104 to the user.

The first riser card 102 is plugged into the first serial connectionexternal interface 124 with avoidance of abutment of the first memorymodule 112, 114 with a second memory module 402, 404 supported by anadjacent riser card.

An exemplary implementation comprises a first riser card 102 thatsubstantially axially connects with a first FB-DIMM connector of aplural number of FB-DIMM connectors on a PCB 104. The first riser card102 comprises a first DDR-DIMM connector that engages a parallelconnection external interface 136, 138 of a first memory module 112,114. A second riser is adjacent to the first riser card 102. The secondriser card 302 comprises a second DDR-DIMM connector that engages aparallel connection external interface 136, 138 of a second memorymodule 402, 404. The first and second riser cards 102, 302 support thefirst and second memory modules 402, 404 with avoidance of abutment ofthe first memory module 112, 114 with the second memory module 402, 404.The first and second riser cards 102, 302 comprise a plurality ofDDR-DIMM connectors that is equal in number to the plural number ofFB-DIMM connectors on the PCB 104. The plurality of DDR-DIMM connectorsof the first and second riser cards 102, 302 comprises the firstDDR-DIMM connector on the first riser card 102 and the second DDR-DIMMconnector on the second riser card 302.

An implementation of the apparatus 100 in an example comprises aplurality of components such as one or more of electronic components,chemical components, organic components, mechanical components, hardwarecomponents, optical components, and/or computer software components. Anumber of such components can be combined or divided in animplementation of the apparatus 100. In one or more exemplaryimplementations, one or more features described herein in connectionwith one or more components and/or one or more parts thereof areapplicable and/or extendible analogously to one or more other instancesof the particular component and/or other components in the apparatus100. In one or more exemplary implementations, one or more featuresdescribed herein in connection with one or more components and/or one ormore parts thereof may be omitted from or modified in one or more otherinstances of the particular component and/or other components in theapparatus 100. An exemplary technical effect is one or more exemplaryand/or desirable functions, approaches, and/or procedures. An exemplarycomponent of an implementation of the apparatus 100 employs and/orcomprises a set and/or series of computer instructions written in orimplemented with any of a number of programming languages, as will beappreciated by those skilled in the art. An implementation of theapparatus 100 in an example comprises any (e.g., horizontal, oblique, orvertical) orientation, with the description and figures hereinillustrating an exemplary orientation of an exemplary implementation ofthe apparatus 100, for explanatory purposes.

An implementation of the apparatus 100 in an example encompasses anarticle. The article comprises one or more computer-readablesignal-bearing media. The article comprises means in the one or moremedia for one or more exemplary and/or desirable functions, approaches,and/or procedures.

An implementation of the apparatus 100 in an example employs one or morecomputer readable signal bearing media. A computer-readablesignal-bearing medium in an example stores software, firmware and/orassembly language for performing one or more portions of one or moreimplementations. An example of a computer-readable signal bearing mediumfor an implementation of the apparatus 100 comprises a memory and/orrecordable data storage medium of the riser card 102, 302 and/or PCB104. A computer-readable signal-bearing medium for an implementation ofthe apparatus 100 in an example comprises one or more of a magnetic,electrical, optical, biological, chemical, and/or atomic data storagemedium. For example, an implementation of the computer-readablesignal-bearing medium comprises one or more floppy disks, magnetictapes, CDs, DVDs, hard disk drives, and/or electronic memory. In anotherexample, an implementation of the computer-readable signal-bearingmedium comprises a modulated carrier signal transmitted over a networkcomprising or coupled with an implementation of the apparatus 100, forinstance, one or more of a telephone network, a local area network(“LAN”), a wide area network (“WAN”), the Internet, and/or a wirelessnetwork.

The steps or operations described herein are examples. There may bevariations to these steps or operations without departing from thespirit of the invention. For example, the steps may be performed in adiffering order, or steps may be added, deleted, or modified.

Although exemplary implementation of the invention has been depicted anddescribed in detail herein, it will be apparent to those skilled in therelevant art that various modifications, additions, substitutions, andthe like can be made without departing from the spirit of the inventionand these are therefore considered to be within the scope of theinvention as defined in the following claims.

What is claimed is:
 1. A process, comprising: performing an upgrade of aserial memory implementation within a printed circuit board (PCB) to aparallel memory implementation outside the PCB through employment of afirst riser card plugged into a first serial connection externalinterface of the PCB, wherein the first riser card is to support a firstmemory module that employs the parallel memory implementation.
 2. Theprocess of claim 1, comprising: providing the PCB to a user as a fielddeployment of the PCB with a fixed distance between the first serialconnection external interface of the PCB and a second serial connectionexternal interface of the PCB; and plugging the first riser card intothe first serial connection external interface of the PCB after thefield deployment of the PCB to the user.
 3. The process of claim 1,comprising: plugging the first riser card into the first serialconnection external interface with avoidance of abutment of the firstmemory module with a second memory module supported by an adjacent risercard.
 4. The process of claim 1, comprising selecting between a serialmemory implementation and a parallel memory implementation for eachserial connection external interface of the PCB.
 5. The process of claim1, wherein the PCB comprises at least one connector and voltageregulator module.
 6. The process of claim 1, wherein the first risercard and a parallel protocol memory module replace the first serialconnection external interface of the PCB.
 7. The process of claim 1,wherein a number of pins of the first riser card enable the first risercard to plug directly into a memory module of the serial connectionexternal interface of the PCB.
 8. A process, comprising: performing anupgrade of a serial memory implementation within a printed circuit board(PCB) to a parallel memory implementation outside the PCB throughemployment of a translator riser card plugged into a first serialconnection external interface of the PCB while maintaining a secondserial connection external interface of the PCB, wherein the translatorriser card is to support a first memory module and the second serialconnection is to support a second memory module.
 9. The process of claim8, wherein the translator riser card includes a notch at both ends ofthe translator riser card.
 10. The process of claim 9, wherein the notchat both ends of the translator riser card is accommodated by an endlatch of the first serial connection external interface.
 11. The processof claim 8, wherein the PCB includes a single serial memoryarchitecture.
 12. A process, comprising: performing an upgrade of aserial memory implementation within a printed circuit board (PCB) to aparallel memory implementation outside the PCB through employment of atranslator riser card plugged directly into each serial connectionexternal interface of the PCB, wherein the translator riser card is tosupport a corresponding memory module for each serial connectionexternal interface of the PCB.
 13. The process of claim 12, wherein thetranslator riser card is to plug directly into a FB-DIMM memoryarchitecture.
 14. The process of claim 13, wherein the translator risercard is to enable a DDR3 SDRAM DIMM memory architecture to be utilizedwith the FB-DIMM memory architecture.
 15. The process of claim 14,wherein a memory bandwidth of the FB-DIMM memory architecture and theDDR3 SDRAM DIMM memory architecture are maintained.